CompuServe Thread

Forum unknown · Hardware

#Memory Expansion

7 messages in this thread
#23606From: Larry Phillips/ICUGJun 20, 1986 10:02 PM
I don't doubt that. What do they do? Segment the RAMs into 57.4K chunks? <grin> The 4502A is the 256K version of the 4500, and I have an application note on the 4500 that just about makes me drool.
#23624From: scott drysdaleJun 20, 1986 10:51 PM
no. what they do is provide no external control over when a refresh gets done (ie, no way to synchronize a refresh with an empty bus cycle). they simply provide select and read/write inputs, and give you a wait signal for output. gag. –Scotty
#23641From: FRANK SCHWABJun 21, 1986 12:33 AM
The THCT4502A DOES provide an external REFREQ* input, meaning that you can disable its internal refresh clock and generate your own refresh cycles when you desire. I don't know how much it will speed up memory access, since when the 68000 is doing a memory read, its generally for the prefetch queue anyway. I think if you try to get much more complex about refresh cycles, you are going to make this 48 pin chip pretty much useless anyway. Ah, well,
#23641From: FRANK SCHWABJun 21, 1986 12:33 AM
The THCT4502A DOES provide an external REFREQ* input, meaning that you can disable its internal refresh clock and generate your own refresh cycles when you desire. I don't know how much it will speed up memory access, since when the 68000 is doing a memory read, its generally for the prefetch queue anyway. I think if you try to get much more complex about refresh cycles, you are going to make this 48 pin chip pretty much useless anyway. Ah, well,
#23668From: Larry Phillips/ICUGJun 21, 1986 3:23 AM
You are right, but then again, the stuff that is needed in addition to the controller looks to be minimal compared to the rat's nest we would have without it.
#23668From: Larry Phillips/ICUGJun 21, 1986 3:23 AM
You are right, but then again, the stuff that is needed in addition to the controller looks to be minimal compared to the rat's nest we would have without it.
#23624From: scott drysdaleJun 20, 1986 10:51 PM
no. what they do is provide no external control over when a refresh gets done (ie, no way to synchronize a refresh with an empty bus cycle). they simply provide select and read/write inputs, and give you a wait signal for output. gag. –Scotty