Allowing arbitrary starting addresses causes an 'adder' to be included in
the logic on all boards and, in general, slows down the access to that
board.
My design used a 74283 adder, but only because I made my board check that
it didn't go beyond 9fffffH. I'd much rather have a second latch programmed
during the autoconfig cycle to represent the ending address to use with a
second comparitor and have the logic: if it's greater than register A and
less than register B then enable the board. No more delay time than the
comparitor plus a PAL to NAND the two signals. It'd probably require the
74S85 comparitor because of it's > = < outputs. Total delay time 11.5ns +
PAL ~= 25 nsec.
Too bad CBM didn't do it that way. If they forced 8 bit decoding then an 8
Meg board could have been configured to 8 Meg minus 64K. -Greg