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It appears the 250 million ops is correct … here is a much more detailed story from PRNewswire … 04/18 0736 MOTOROLA UNVEILS 32-BIT 68060 PRODUCT LINE OF … – Motorola's (NYSE: MOT) High Performance Microprocessor Division today formally introduced the 68060 product line of microprocessors. The first generation of the 68060 product line consists of the 68060, 68LC060 and 68EC060. The announcement of the 68060 marks a revolutionary high-point in the evolution of Motorola's 68000 Family. Leveraging many of the same performance enhancements used by RISC designs as well as providing innovative architecturial techniques, the 68060 harnesses new levels of performance for the 68000 Family. Key benefits such as hardware and software compatibility with 68040 designs, cost-effective memory systems requirements and an extremely power efficient architecture makes the 68060 an ideal processor choice for a broad range of networking/communication, telecommunication and control applications. With 68000 Family code compatibility, the 68060 provides a range of upgrade opportunities to virtually any existing 68040 application. Incorporating 2.5 million transistors on a single piece of silicon, the 68060 employs a deep pipeline, dual issue superscaler execution, a branch cache, a high performance floating point unit, 8 Kbytes each of on-chip instruction and data caches and on-chip demand paging memory management units (MMUs). It allows simultaneous execution of two integer instructions (or an integer and a float instruction) and one branch instruction during each clock period. All integer arithmetic or logical instructions are able to perform an embedded load/store operation making the 68060 capable of simultaneously processing up to 250 million operations per second at 50-MHz. The 68060 delivers an average performance level of 90 VAX MIPS at 50-MHz. "The introduction of the 68060 affirms Motorola's commitment to the ongoing success of the 68000 Family and our willingness and ability to field competitive product technology," said Cal Gooden, director of operations, Motorola High Performance MPU Division. "Outstanding performance for cost-constrained systems makes the 68060 microprocessor an ideal choice for embedded applications. We are pleased to have such customers as Force Computers, Heurikon, Motorola Computer Group and Wellfleet be the first supporting the 68060." Scalable Superscalar Architecture Employing high-level synthesizable modeling, coupled with strict partitioning of functionality, the 060 represents a platform for the proliferation of high-performance embedded computing. The first generation of the 060 product line are distinguished by the use of dual integer pipelines, dedicated branching unit, optional floating point processor and the rich instruction-set of the 68040 architecture. The 060 can be easily modified for higher performance implementations as well as provide substantially cost-reduced versions through the manipulation of the 060's high-level model. Pursuing a strategy of re-use and incremental improvement, Motorola expects to rapidly deploy the 060 technology to a wide range of price/performance points. The 68060 features a full internal Harvard architecture. The instruction and data caches are designed to support concurrent instruction fetch and operand read and operand write references on every clock cycle. Separate 8 Kbyte instruction and 8 Kbyte data caches can be frozen to prevent allocation over time-critical code or data. The independent nature of the caches allows instruction-stream fetches, data- stream fetches and external accesses to occur simultaneously with instruction execution. The operand data cache is four-way banked to permit simultaneous read and write access in each clock. A very high bandwidth internal memory system coupled with the compact nature of the 68000 Family code allows the 060 to achieve extremely high levels of performance even when operating from low-cost memory such as a 32-bit wide DRAM memory system. Instructions are fetched from the internal cache or external memory by a four stage instruction fetch pipeline. The 68060 variable-length instruction system is internally decoded into a fixed length representation and channeled into an instruction buffer. The instruction buffer acts as a FIFO which provides a decoupling mechanism between the instruction fetch unit and the operand execution units. Fixed Format Instructions are dispatched to dual four-stage pipelined RISC operand execution engines where they are then executed. In addition to the performance gains from this superscalar execution architecture, a brand cache plays a major role in achieving the high performance levels of the 68060. The branch cache has been implemented such that most branches are executed in zero cycles. Using a technique known as branch folding, the branch cache allows the instruction fetch pipeline to detect and change the instruction prefetch stream before the change of flow affects the instruction execution engines, minimizing the need for pipeline refill. The 68060 Product Line Features and Performance The first generation 68060 product line offers three versions. The 68060, 68LC060 and the 68EC060 differ in the feature offerings only. All three microprocessors offer a performance level of over 100 MIPS at 66-MHz. The 68060 comes fully equipped with both an FPU and MMU for high-end embedded control and desktop applications. For cost sensitive embedded control and desktop applications where designers need an MMU but don't want to pay for an FPU, the 68LC060 offers high-performance at a low cost. Specifically designed for low-cost embedded control applications the 68EC060 comes without both the FPU and MMU permitting designers to leverage 68060 performance while avoiding the cost of unnecessary features. Power Management In addition to substantial cost and performance benefits, the 060 also offers advantages in power consumption and power management. The 68060 automatically minimizes power dissipation by using a fully- static design, dynamic power management and low voltage operation. Each stage of the integer unit pipelines and the FPU pipeline draws power only when an instruction is executing and the cache arrays draw power only when an access is made. Explicitly the 68060 power consumption can be controlled from the operating system. For example, the 060 includes a low-power stop instruction (LPSTOP) that shuts down the active circuits in the processor, halting instruction execution and greatly reducing power consumption. Although the 68060 operates at a lower operating voltage, it interfaces to both 3V and 5V peripherals and logic. To assist in product design, a broad base of established development tools is available for the 68060 including: applications, assemblers, compilers, debuggers, languages, operating systems and real-time kernels. Note that the accompanying 68060 third party developer support news release explicitly outlines the tool offering. The 50-MHz 68060, 68LC060, and 68EC060 are currently sampling to alpha and beta sites. General samples will be available for both the 50- MHz and 66-MHz 68060 by 3Q94. Production for the 50-MHz 68060 is slated to start in late 3Q94. While production for the 66-MHz 68060 will begin in late 4Q94. The 50-MHz 68060 is priced at $263 in quantities of 10,000. The 68LC060 and the 68EC060 are priced at $169 and $150 in quantities of 10,000 respectively. Having 1993 worldwide sales of $5.7 billion, Motorola's Semiconductor Products Sector is the largest U.S.-based broad line supplier of semiconductors, with a balanced portfolio of more than 50,000 devices. Motorola is one of the world's leading providers of wireless communications, semiconductors, and advanced electronic systems and services. Major equipment businesses include cellular telephone, two-way radio, paging and data communications, personal communications, automotive, defense and space electronics and computers. Communication devices, computers and millions of consumer products are powered by Motorola semiconductors. Motorola's 1993 sales were $17 billion. -0- 4/18/94 /CONTACT: Kathleen Kenney or Samantha Rutherford of Cunningham Communication, 617-494-8202; or Tom Spohrer of Motorola, 512-891-2917/ (MOT) CO: Motorola, Inc. ST: Texas IN: CPR SU: PDT