CompuServe Messages

> Another thing discussed by Motorola is the fact that 100Mhz and > 200Mhz versions of the '060 will be available with the 200Mhz > version giving ~450 VAX MIPS. 200Mhz over a 32 bit bus! That will be fun to watch! What a waste of Mhz. It will sit there and idle waiting for memory 50% of the time. 🙁 Interleaving is a poor solution when the CPU has to stall for _huge_ amounts of time. The instant you leave the small cache (8K instruction), your CPU will stall for a very long time. What will you do, 8 times interleave? Moto has talked very openly about high clocked PowerPC but EE Times questioned Motos intrest in a high clock '060. They will barely ship a 66Mhz this year. How long will it be until 100Mhz? The critical paths in the '060 are almost certainly fairly long. A glance at instruction timings could allow a guess. When Moto and IBM went from POWER to PowerPC they droped the ABS instruction because it would have required a simple multiplexer in the critical path which would have lengthened cycles by as little as a nano-second! It may not seem like much but, in the end, the CPU would have been 10% slower! The '060 did not have the luxury of redfining the instruction set and simply discarding what would slow the CPU down! I hope we see one, but considering how late the '060 was I would not hold my breath! Want to formalize my $1 bet that the fastest shipping PowerPC will always be twice as fast as the fastest shipping '060 averaging SPECint and SPECfloat from Moto's offical numbers together? <GRIN> —– Andrew