CompuServe Messages

–jp–seattle– I puzzled over the 'how-to-do' part quite a lot last year. Can't remember all the details anymore, but I seem to recall that the only real nastiness involved is in preventing RAM contention. You hafta make a globally acessable table showing what memory is locked out, and set it up so that only one CPU can access it at once. Memory is addressed linearly, but each CPU has a mem bank reserved for its use: looks like this– MASTER CPU SLAVE #1 SLAVE #2 SLAVE #3 ….. 0-16M 16-20M 20-24M 24-28M ….. ..not that all of the memory need be installed, but less than 1Meg per CPU would be a waste. The master would need a few Meg extra. When the 680×0 in slave #1 makes a read to its own memory bank, the higher bits of the address indicate a 'local' read and the data is gotten from the slave's internal bus. No bus contention, therefore. External reads have different bits in the high end, and now the chip has to request bus access. The OS needs to be tweaked to get progs to use RAM inside their own bank as much as possible. Every read/write to other mem banks including the master bank slows the system down. Another version I came up with relied on a 'phasic' bus. This bizarre creature required a 114.04MHz bus & 16 680×0's. Could never get any of my E/E friends to buy into the idea as it had horrible switching problems, but from the OS standpoint, it looked feasible. Would've appeared to the user to be 16 Amiga's in one box, all thinking that they were independant machines, despite having overlapping memory and shared hardware. Nifty stuff, but way too weird. Each 680×0 would THINK that it was the master and all the others were slave chips… No, it can be done, but would it sell in Topeka? ————————————————————TL———-