CompuServe Messages

Bela– Here is some more info on the 68030. The new stuff for the 68030 includes: data cache as well as the 68020's instruction cache, built in MMU that is program compatible with the 68851, and an enhanced bus controller. The data cache works the same as the 020's instruction cache with the addition of data write through for writes. The MMU is a paged MMU with the same functionality of the 68851 but without the 1 cycle or so speed penalty you get with the seperate 68851 chip. The bus controller can support a burst mode that works with DRAMs out now that have a nibble mode. They give the first data in normal access time but then can hand over up to 3 more bits from sequential addresses using the chip's nibble mode. At max bus speed the 030 can fetch 16 bytes in 5 clock cycles (200ns). This is used to advantage for cache misses to catch up and get ahead of cpu again. Memory accesses go in parallel to the MMU and the caches. If the cache hits the MMU memory access is aborted. The CPU can simultaneously calculate the effective addresses of a data operand and the next program stream fetch, as well as execute a data manipulation operation in the ALU. At the same time the CPU may also be fetching a data operand fom the data cache and an instruction word from the instruction cache. All five of these events plus a bus interface unit write to external memory may occur at the same time. The only time the MMU causes any time delay is if it fails to hit the paging cache. (they predict 99% hit ratio for typical operation). All of this from a Motorola article in Oct 1 Electronic Products mag. They quote samples available now for $350 with production quantities in the spring. I don't know whether to believe this or the EE Times article on schedule.