CompuServe Messages

Jim, Your analogy to MPG ratings is way off base. Citing MIPS as a performance figure, assuming that by MIPS you mean the number of _native_ instructions per second, is not at all like citing MPG rates for vehicles, simply because a mile is a mile, and a gallon is a gallon. In the case of a CPU chip, and instruction is only an instruction for that specific CPU chip, and it is handled in different ways in different architectures. Citing MIPS as a raw figure, is the logical equivalent to saying "My car gets 60 distance units per fuel amount unit", wihtout specifying what the units are. RISC chips don't have complex instructions, and in general, execute one instruction per clock cycle. To compare that with a CISC chip, with both simple and complex insrtructions, some of which _may_ execute in a single clock cycle, some of which may take many tens of cycles, is an excercise in futility, giving results that are not even close to being meaningful. Similarly, the instruction sets of two different architectures of CISC chips are likely to be different, in both capabilty and in the number of cycles taken per instruction. Similar, meaningless comparisons are obtained by quoting MIPS. This does not take into account that MIPS is sometimes quoted only on the fastest instructions, and sometimes on the whole set, an sometimes on what the manufacturer deems to be a 'representative subset'. MFLOPS is a whole lot closer to being meaningful, if for no other reason than that it is limited in the scope of operations performed, and that those operations are more complex, requiring many more clock cycles in both CISC and RISC chips. But of course, it is only a measurement of a limited part of a CPU chip's repertoire. -larry