CompuServe Messages

Well, I do agree that in the MIPS measurement, there is one known, and quantifiable factor; that being the unit if time, the SECOND. Instructions, as I have pointed out, are not quantifiable without considerable further qualification. That qualification must include architecture, which insctructions are being used (a subset or the entire set), how many clock cycles are taken for each one, and how much 'work' is done by each one. The clock cycle speed and the number of instructions done per cycle also needs further qualification. It is quite possible for a CPU to perform more than one instruction per clock cycle, as evidenced by the latest RISC chips from IBM. Note, however, that the IBM chip does not have a fixed, immutable MIPS rate, since it depends entirely on the exact sequence and mix of instructions. IBM of course, chooses its tests carefully. The customer has no such option. In short, MIPS is no more a valid comparison than raw clock speed. One might as well measure the cabinet and quote a performance figure per cubic inch. The ONLY value of MIPS comes in rating chips whose architectures are VERY similar, which comes in handy for rating faster chips from the same manufacturer, though there are sometimes enough dissimilarities to throw those comparisons off. I'm probably a little too vehement in my arguments on this, but it's one of my 'hot buttons'. I have gone through this argument many times, with Intel bigots who just could not see that raw clock speed does not reflect performance in widely differing chips, and with folks who thought that seek times were the only criteria for disk throughput comparisons. So… on to eigenvalues (don't even know what they are), and Lemmings (never played it). 🙂 -larry