#68060
Motorola says they are finishing the RISC implementation of the instruction
set in the '060, and adding superscaler. That should result in a lot of
speed when runing out of cache, and a massive degradation on cache misses.
The caches are to be larger as well. This should result in a best case
performance of about 2.5X at the same clock speed. This is from
information received at the Motorola Educational Conference.
Gary Dunlap : Wyrd Software
: It just works like magic!