CompuServe Messages

I would think that if you are in the middle of a refresh cycle, and the CPU has asserted AS*, then you must do a little more than just allow things to "just happen". The problem is that by the time you are done your refresh, the CPU is liable to be in "wait" clock cycles. As soon as you let go of XRDY, the CPU will proceed to S6, and at the falling edge of S6, will expect data to be valid. I think, therefore, you will have to "fake" a full cycle, gating the address lines, etc, and let go of XRDY at the appropriate time (as if it was never asserted, but giving the data time to be there.). We are currently looking at the feasibility/cost of a DRAM controller. Simplifies things a LOT! There is a TI chip for 64K memories available for about $15.00 US, and I know there is a 256K equivalent, so we are checking that angle out. In the 64K implementation, it is possible to get by with the RAMs and the controller only. The example in the data book shows a 256K memory organized as two banks of 128K * 16.