CompuServe Messages

The 68000 handles data transfers asynchronously. It does not require that a read or write transpire in a fixed number of clock cycles. Instead it requires a transaction acknowledgement, a handshake named DTACK, from whatever peripheral it is dealing with. This feature means that the 68K can access memory of varying speeds, so long as the memory design provides the DTACK signal when the memory data is valid. The 68K read and write operations may be described most clearly as finite state machines clocked by both edges of the processor input clock. DTACK is sampled as an input to those machines. 68K reads and writes are slightly different, but in both cases if the handshake DTACK isn't true after the default read or write cycle time, then the 68K passes through two wait states lasting a total of one clock cycle. DTACK is again sampled; this process is repeated until DTACK becomes true, then the read or write passes through a few more states to completion. NMOS DRAM must be refreshed because it is composed of pass transistor logic, gating packets of electrical charge to and fro on a piece of glass. A single bit of NMOS memory most resembles a leaky capacitor made of a FET. The refresh operation is merely that of reading the memory cell output, and feeding it back to the input to recharge the capacitor. Actually a whole array of bits is at once refreshed in this manner. And most memories specify that each bit must be refreshed at 2 to 4 millisecond intervals. Otherwise the memory will literally leak away. One challenge facing memory designers is that of handling refresh non obtrusively, giving the CPU and DMA devices as much access as possible. When a computer bus is properly terminated to minimize noise, and all access buffered, there is a small but significant delay between the time processor address lines become valid for the next bus operation, and the time the bus peripheral devices actually see the valid addresses. The same is true of the data bus connecting the processor to the peripheral. Those delays must be added to the delays called memory chip access time, and some of lesser magnitude, to determine how long memory access actually takes. The longer this takes, the higher the likelihood that wait states will be inserted by the 68000. 68000 systems usually have 0 wait state memory only on the same board as the 68K itself, physically very close. Path delays usually force the insertion of wait states to guarantee valid I/O to other boards on the bus. The point of all this is that wait states occur for a number of reasons, not merely because of refresh. A buzzing in my brain tells me that Commodore was optimistic when they stuck that 68K directly on the expansion bus. Capacitive loading and noise may cause problems if sidecar is used with any other devices betwixt the sidecar and amiga. regards, Jim Nelson Chrysalis Microsystems