I meant in your gate array version (Akiko) you could add a turbo-version of a
PIA interface that you switch to by adding a bit somewhere.. The defaut of this
bit would be the normal PIA that you have now, but setting this bit would gain
acess to a faster interface..(more circuitry).. I was wondering what your input
was to the gate array vender.. was it a schematic based, or was it written in
VHDL?(Visic Hardware Design Language) If the vendor was VLSI tech It probably
was a "soft" macro.. (the timing changes with each layout).. I am just curious
is all..
-Tom-