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#86 pin vs 100 pin
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I am a worried person.I have been reading the new amigaworld mag and
looking at all the expansion products.My question: I got my amiga in Nov 85
and the ads all mention they work under a 100 pin bus( wording?).Now I seem
to recall something about the early amigas having 86 pins and I think mine
has that.What is a person supposed to do if this is true and the products
work with 100 pin connectors?Allso, what is 'no wait state' in regards to
memory expansion? Thanx, Michael Cohoon 70107,1670
Not to worry………
The 100 pin expansion they are talking about is for external devices
designed to accept plug in cards. Such as an expansion box, the box itself
will have the 86 pin interface to the Amiga, but the slots in the box for cards
will have a 100 pin plug in that conforms to CA specs.
0 wait states means that memory refresh of the RAM is done in such a
way that it doesn't tell the 68000 to "wait" while it is doing a memory
refresh. RAM, specifically Dynamic RAM (DRAM) has to be refreshed every so
often (actually quite often, as on the order of several times per second) and
some expansion designs require the 68000 to stop it's processing while the
refresh is going on. 0 wait refresh does the refresh in such a way that the
68000 does not have to stop.
The 68000 handles data transfers asynchronously. It does not require that
a read or write transpire in a fixed number of clock cycles. Instead it
requires a transaction acknowledgement, a handshake named DTACK, from
whatever peripheral it is dealing with. This feature means that the 68K
can access memory of varying speeds, so long as the memory design provides
the DTACK signal when the memory data is valid.
The 68K read and write operations may be described most clearly as finite
state machines clocked by both edges of the processor input clock. DTACK
is sampled as an input to those machines. 68K reads and writes are
slightly different, but in both cases if the handshake DTACK isn't true
after the default read or write cycle time, then the 68K passes through two
wait states lasting a total of one clock cycle. DTACK is again sampled;
this process is repeated until DTACK becomes true, then the read or write
passes through a few more states to completion.
NMOS DRAM must be refreshed because it is composed of pass transistor
logic, gating packets of electrical charge to and fro on a piece of glass.
A single bit of NMOS memory most resembles a leaky capacitor made of a FET.
The refresh operation is merely that of reading the memory cell output, and
feeding it back to the input to recharge the capacitor. Actually a whole
array of bits is at once refreshed in this manner. And most memories
specify that each bit must be refreshed at 2 to 4 millisecond intervals.
Otherwise the memory will literally leak away.
One challenge facing memory designers is that of handling refresh non
obtrusively, giving the CPU and DMA devices as much access as possible.
When a computer bus is properly terminated to minimize noise, and all
access buffered, there is a small but significant delay between the time
processor address lines become valid for the next bus operation, and the
time the bus peripheral devices actually see the valid addresses. The same
is true of the data bus connecting the processor to the peripheral. Those
delays must be added to the delays called memory chip access time, and some
of lesser magnitude, to determine how long memory access actually takes.
The longer this takes, the higher the likelihood that wait states will be
inserted by the 68000.
68000 systems usually have 0 wait state memory only on the same board as
the 68K itself, physically very close. Path delays usually force the
insertion of wait states to guarantee valid I/O to other boards on the
bus.
The point of all this is that wait states occur for a number of reasons,
not merely because of refresh.
A buzzing in my brain tells me that Commodore was optimistic when they
stuck that 68K directly on the expansion bus. Capacitive loading and noise
may cause problems if sidecar is used with any other devices betwixt the
sidecar and amiga. regards, Jim Nelson Chrysalis Microsystems
The 68000 handles data transfers asynchronously. It does not require that
a read or write transpire in a fixed number of clock cycles. Instead it
requires a transaction acknowledgement, a handshake named DTACK, from
whatever peripheral it is dealing with. This feature means that the 68K
can access memory of varying speeds, so long as the memory design provides
the DTACK signal when the memory data is valid.
The 68K read and write operations may be described most clearly as finite
state machines clocked by both edges of the processor input clock. DTACK
is sampled as an input to those machines. 68K reads and writes are
slightly different, but in both cases if the handshake DTACK isn't true
after the default read or write cycle time, then the 68K passes through two
wait states lasting a total of one clock cycle. DTACK is again sampled;
this process is repeated until DTACK becomes true, then the read or write
passes through a few more states to completion.
NMOS DRAM must be refreshed because it is composed of pass transistor
logic, gating packets of electrical charge to and fro on a piece of glass.
A single bit of NMOS memory most resembles a leaky capacitor made of a FET.
The refresh operation is merely that of reading the memory cell output, and
feeding it back to the input to recharge the capacitor. Actually a whole
array of bits is at once refreshed in this manner. And most memories
specify that each bit must be refreshed at 2 to 4 millisecond intervals.
Otherwise the memory will literally leak away.
One challenge facing memory designers is that of handling refresh non
obtrusively, giving the CPU and DMA devices as much access as possible.
When a computer bus is properly terminated to minimize noise, and all
access buffered, there is a small but significant delay between the time
processor address lines become valid for the next bus operation, and the
time the bus peripheral devices actually see the valid addresses. The same
is true of the data bus connecting the processor to the peripheral. Those
delays must be added to the delays called memory chip access time, and some
of lesser magnitude, to determine how long memory access actually takes.
The longer this takes, the higher the likelihood that wait states will be
inserted by the 68000.
68000 systems usually have 0 wait state memory only on the same board as
the 68K itself, physically very close. Path delays usually force the
insertion of wait states to guarantee valid I/O to other boards on the
bus.
The point of all this is that wait states occur for a number of reasons,
not merely because of refresh.
A buzzing in my brain tells me that Commodore was optimistic when they
stuck that 68K directly on the expansion bus. Capacitive loading and noise
may cause problems if sidecar is used with any other devices betwixt the
sidecar and amiga. regards, Jim Nelson Chrysalis Microsystems
Not to worry………
The 100 pin expansion they are talking about is for external devices
designed to accept plug in cards. Such as an expansion box, the box itself
will have the 86 pin interface to the Amiga, but the slots in the box for cards
will have a 100 pin plug in that conforms to CA specs.
0 wait states means that memory refresh of the RAM is done in such a
way that it doesn't tell the 68000 to "wait" while it is doing a memory
refresh. RAM, specifically Dynamic RAM (DRAM) has to be refreshed every so
often (actually quite often, as on the order of several times per second) and
some expansion designs require the 68000 to stop it's processing while the
refresh is going on. 0 wait refresh does the refresh in such a way that the
68000 does not have to stop.
No problem here. The 100 pin (Zorro) cards are based on the spec for an
expansion BOX. Every Amiga has the 86 pin edge card, and the bus that's
passed from box to box is always 86 pin. The Amiga system supports, in
hardware and software, two levels of expansion — the "box", which can be
your basic slotted expansion box, or just an add-on memory board, and the
"card", which is something that plugs into a box (I forget the exact Amiga
terms for these).
The extra pins on the 100 pin board are used for communications within the
box. You are correct in your observation that this specification came out
a while after the Amiga, but that has no impact on you Amiga itself. If
you buy a "box", make sure that if it has slots, they are 100 pin slots.
Every box will connect to the Amiga OK. There were a few cards made with 86
pins by some early developers; as far as I've heard, these will fit in a
100 pin slot OK (though I'm not sure how immune to slipping they're likely
to be … the 100 pin slots have no mechanical stops at the 86 pin mark).
As for RAM, the term "no wait states" means that the 68000 will never slow
down when accessing this memory. Most memory expansions use dynamic RAM
devices that must have their internal charges in every memory location
refreshed evey so often, usually once every 4 milliseconds or so. A wait
state can occur if a board decides to refresh this memory at the same time
the 68000 needs it.
There are various methods of design that will insure that this situation
never happens, though this may cause an increase in the price of the
board. Even a board that has potential wait states isn't likely to slow
you down that much, but every bit of speed is a nice thing to have. -Hazy
No problem here. The 100 pin (Zorro) cards are based on the spec for an
expansion BOX. Every Amiga has the 86 pin edge card, and the bus that's
passed from box to box is always 86 pin. The Amiga system supports, in
hardware and software, two levels of expansion — the "box", which can be
your basic slotted expansion box, or just an add-on memory board, and the
"card", which is something that plugs into a box (I forget the exact Amiga
terms for these).
The extra pins on the 100 pin board are used for communications within the
box. You are correct in your observation that this specification came out
a while after the Amiga, but that has no impact on you Amiga itself. If
you buy a "box", make sure that if it has slots, they are 100 pin slots.
Every box will connect to the Amiga OK. There were a few cards made with 86
pins by some early developers; as far as I've heard, these will fit in a
100 pin slot OK (though I'm not sure how immune to slipping they're likely
to be … the 100 pin slots have no mechanical stops at the 86 pin mark).
As for RAM, the term "no wait states" means that the 68000 will never slow
down when accessing this memory. Most memory expansions use dynamic RAM
devices that must have their internal charges in every memory location
refreshed evey so often, usually once every 4 milliseconds or so. A wait
state can occur if a board decides to refresh this memory at the same time
the 68000 needs it.
There are various methods of design that will insure that this situation
never happens, though this may cause an increase in the price of the
board. Even a board that has potential wait states isn't likely to slow
you down that much, but every bit of speed is a nice thing to have. -Hazy